1. Field of the Invention
The present invention relates to a test mode circuit of a semiconductor device and, more specifically, to a test mode circuit of a semiconductor device capable of reducing the number of test lines.
2. Discussion of Related Art
In general, a yield falls off due to a trend toward a high-capacity semiconductor memory, the possibility that inner defects of a chip are generated is increased due to an increase of a chip area, and the possibility that one or more wires are connected to one defect is highly increased due to a decrease of space between wires by fineness thereof. Specifically, in manufacturing a memory semiconductor integrated circuit, which has field effect transistors (FETs) as main elements, characteristics of the respective layers of the semiconductor integrated circuit are tested in the course of manufacture thereof to guarantee operation of the semiconductor integrated circuit. However, it costs a great deal to test the characteristics of the semiconductor integrated circuit in the course of manufacture of the semiconductor integrated circuit, and a ratio of the test cost to the whole manufacture cost is not negligible. Most of the test cost is expenses for using test devices, and depreciation cost and incidentals are also included in the test cost.
Also, the test time gets increased with enhancement of the degree of integration. But, at present, in order to enhance the manufacture reliability, an increase of the test time is prevented by lowering the degree of integration to reduce test dependency of the product reliability.
In view of such situations, it is a long-range goal in the related art to reduce the test cost, and various kinds of methods are examined for the purpose thereof. For example, a plurality of parallel tests are executed to reduce equipment cost, and in this case, high incidental expenses are not only required, but also an expensive high-speed tester is required.
One control circuit and one test line are used for one test item in a case where a DRAM uses a test mode. As a result, the test lines should be arranged in the limited area in designing the layout. Therefore, addition of a test item causes increases of lines in a full chip area.
The conventional method will be explained with reference to FIGS. 1 to 3.
A test mode control unit 10 is connected to a test mode utilizing unit 30 such as a voltage level control circuit or a pulse width control circuit through a test mode line 20. The test mode control unit 10 comprises a plurality of decoders 40a to 40n as shown in FIG. 2. In a state where a test start signal Test—start is enabled, when address codes Add<0> to Add<n> which are predetermined corresponding to items to be tested are inputted, output signals of the decoders 40a to 40n corresponding to the input address codes are changed to a high state from a low state. As a result, the test mode signals Test—mode<0> to Test—mode<n> are generated. The test mode signals are inputted to the test mode utilizing unit 30 through the corresponding test mode lines, and a checking signal Check—signal is inputted to test mode identifying units 50a to 50n. 
According to the conventional method, there is a problem that the chip area is increased because one test mode line is required for one test mode as described above.